1. Field of the Invention
The present invention relates to a processing apparatus comprising a plurality of operating units which share at least one register file.
2. Description of the Prior Art
In a data processing apparatus including two or more operating units, each of the two or more operating units and a register file are electrically connected to each other via a plurality of bus lines through which data transfer between each of the operating units and the register file is carried out. The plural operating units and the register file are arranged such that they are aligned in only a specified direction and each of the operating units are connected with the register file via a plurality of data bus lines.
Referring now to FIG. 18, there is illustrated a block diagram showing the structure of a prior art processing apparatus provided with three operating units. In the figure, each of reference numerals 10, 20, and 30 denotes an operating unit. Furthermore, reference numeral 40 denotes a register file comprised of a plurality of registers. The operating unit 10 and the register file 40 are electrically connected to each other via a data bus 11. The operating unit 20 and the register file 40 are electrically connected to each other via a data bus 21. Furthermore, the operating unit 30 and the register file 40 are electrically connected to each other via a data bus 31.
In the above configuration as shown FIG. 18, the data bus 31 between the register file 40 and the operating unit 30 is arranged such that it is running across the operating unit 20 and therefore its wiring length is longer than those of the other data buses. Each of the operating units can include a single-function block such as an arithmetic unit (ALU) or a shifter, or a relatively large-scale block constructed of a cluster of those single-function blocks. Thus, as the number of operating units is increased, the lengths of bus lines connecting each of the operating units with a register file are increased, as a corollary to an increase in the number of the operating units, and therefore loads on the processing apparatus such as parasitic capacity and resistance is increased. This results in causing a bottleneck to speeding up of the chip, reduction of power consumption, and improvement in the reliability of such the processing apparatus.
Such the prior art processing apparatus having the above-mentioned structure suffers from the problem that since as the number of operating units is increased the lengths of bus lines connecting each of the operating units with a register file are increased and therefore loads on the processing apparatus such as parasitic capacity and resistance are increased, an increase in the number of operating units causes a bottleneck to speeding up of the chip, reduction of power consumption, and improvement in the reliability of the processing apparatus.